There is a clock data recovery circuit that recovers clock signals from burst data signals. Such a data and clock receiver circuit is disclosed in JP-A-Hei2(1990)-56134.
According to the clock data recovery circuit disclosed by JP-A-Hei2(1990)-56134, a binary quantization comparator is used to check received burst signals and sampling clocks to determine whether their phases are early or late respectively. If the number of any of “early” and “late” determinations reaches a preset threshold value N, the comparator moves the sampling clock phase by a ±M value. And in order to shorten the bit synchronization time between burst data signals and sampling clocks, if the number of any of “early” and “late” determinations reaches the preset threshold value N upon starting burst signal receiving, the comparator moves the sampling clock phase by an M value (quick mode) and if the number of any of “early” and “late” determinations reaches the preset threshold value N after determining that the synchronization with burst data signals is established, the comparator moves the sampling clock phase by an M′ value (continuous mode). The relationship between M and M′ is assumed as M>M′. And if detecting a phase difference upon starting burst data receiving, the comparator adjusts the phases significantly to realize quick bit synchronization.